1. Field
Clock synchronization in microelectronic circuit design.
2. Background
Integrated circuits such as processors, memory devices, and input/output (I/O) devices typically communicate with each other using digital data signals and clock signals. Some systems use a “clock forwarding” technique where a device that sources digital data signals also sources the associated clock signal. The clock signal is then used at the receiving device to time the received data.
FIG. 1 is a block diagram of a simplified prior art system 100 that uses a forwarded clock. System 100 includes integrated circuits 110 and 150 coupled by conducting lines 120 and 122. Only an output interface of circuit 110 and an input interface of circuit 150 are shown. Circuit 110 includes a driver 112 to drive clock signals on line 120 and a driver 114 to drive digital data signals on line 122. Circuit 150 includes input drivers 154, 152 to receive the incoming clock and data signals, respectively. The incoming clock signal, after distributed by a receiver (RX) clock tree 156 is received by a sequential element 158 that includes a plurality of flip-flops. On each clock pulse, sequential element 158 samples the incoming data signals and outputs a data symbol to downstream logic 160 (not drawn to scale). To correctly sample the received data, it is often required that the sampling clock edge be aligned with the center of a data eye pattern within a relatively small range of tolerance.
To ensure the alignment of the clock and data signals, a link training process may be performed after power-on or reset. Typically, a specific data pattern, called a training sequence, is sent from circuit 110 to circuit 150 during the link training. For example, circuit 150 may receive the training sequence, and retransmit the sequence back to circuit 110 using an output interface of circuit 150 and an input interface of circuit 110 not shown in FIG. 1. According to the feedback training sequence, circuit 110 may adjust the phases of its transmitter (TX) clock and data so that these signals are phase matched when received by circuit 150. Additional timing adjustment may be performed to phase match the data with the clock signals at the input of sequential element 158.
However, the received clock at the input of sequential element 158 may drift from the aligned position after the initial training. For example, RX clock tree 156 may be subject to voltage or temperature variations. As a result, propagation delays introduced by RX clock tree 156 may slowly change. Thus, in some conventional systems, a training sequence similar to the one described above is periodically transmitted to ensure the alignment of data and clock signals.